1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the present invention relates to a digital phase interpolator for controlling fine delay time of a semiconductor integrated circuit and a method thereof.
2. Description of the Related Art
A semiconductor integrated circuit usually employs a circuit for controlling fine delay time. Often a digital phase interpolator is used to control delay times of internal clock signals in a semiconductor integrated circuit.
FIG. 1 illustrates a circuit diagram of a digital phase interpolator for controlling delay time according to the prior art. The conventional digital phase interpolator is comprised of inverters 100, 105 and first-third delay stages 110, 120, 130. FIG. 1 indicates the digital phase interpolator having 9-minimum delay steps.
Referring to FIG. 1, the inverters 100, 105 invert a first signal (IN1) and a second signal (IN2) respectively, and output inverted signals. First signal (IN1) and second signal (IN2) have different phases. Then, inverters 112, 114 of the first delay stage 110 invert an output signal of the inverter 100, and inverters 116, 118 of the first delay stage 110 invert an output signal of the inverter 105. The inverters 114, 116 blend phases of the first signal (IN1) and the second signal (IN2), generate a phase blending signal having an intermediate phase between the phases of the two signals (IN1, IN2), and apply the phase blending signal to the second delay stage 120.
If the number of minimum delay steps is nine as in the example above, the second delay stage 120 and the third delay stage 130 are comprised of more inverters than those of the first delay stage 110. Thus, the number of output signals of each stage increases compared to that of the previous stage. The number of output signals of the second delay stage 120 is five and the number of output signals of the third delay stage 130 is nine. That is, a total of 24-inverters are required to design a phase interpolator having 9-steps. The number of inverters required for the I-th delay stage (except the first delay stage) may be determined by the equation: N(I)=2*N(Ixe2x88x921)xe2x88x921, where N(Ixe2x88x921) indicates the number of inverters in the previous delay stage.
FIG. 2 illustrates a diagram of a process in which output signals from the circuit shown in FIG. 1 are generated, and the number of output signals generated from each of the delay stages 110-130 increases for each consecutive stage. Referring to FIG. 1 and FIG. 2, one of third delay stage 130 output signals (D1-D9) is selected and becomes an output signal (SOUT).
If minimum delay steps are reduced to obtain high resolution, the number of blocks, such as inverters for phase blending, is increased. Also, because the number of output signals outputted from each delay stage increases as the number of delay stages increases, current dissipation of the total circuit is increased. Moreover, it is difficult to match loading of internal inverters of each delay stage to have linear output characteristics of phase delay control. If loading matching is needed, the number of inverters actually required increases and circuit area may necessarily be increased further. Consequently, current dissipation and the linear output characteristics of a conventional digital phase interpolator are inefficient.
According to a feature of an embodiment of the present invention, there is provided a digital phase interpolator for controlling delay time in a circuit that is capable of reducing circuit area and current dissipation in an integrated circuit as compared to a conventional digital phase interpolator, and is capable of allowing linear output characteristics by selecting axes for interpolation in advance and transferring the axes to a next stage.
According to another feature of an embodiment of the present invention, there is provided a method for controlling delay time of the digital phase interpolator.
According to a feature of an embodiment of the present invention, a digital phase interpolator is provided which includes a plurality of delay stages to control a delay time of an output signal from a first and a second signal of differing phase delays. The plurality of delay stages are connected serially to each other, have a same internal structure, and determine corresponding axes for interpolation in each stage. Also, each of the plurality of delay stages includes a first inverting section, a phase blender, a second inverting section, and a multiplexer. The first inverting section inverts a first and a second input signal inputted from the previous stage. The phase blender generates a phase blending signal by phase blending output signals of the first inverting section. The second inverting section inverts the output signals of the first inverting section. The multiplexer generates input signals for a next stage by determining one of output signals outputted from the second inverting section and the phase blending signal as axes for interpolation in response to a selection signal for determining phase delay time of an output signal of the digital phase interpolator.
According to another feature of an embodiment of the present invention, a method for controlling a delay time of an output signal of a phase interpolator having a plurality of delay stages connected serially to each other and having a same internal structure for interpolation of a first and a second signal having different phase delays is provided which includes generating a plurality of phase blending signals corresponding to each delay stage by phase blending an output signal resulting from a first and a second input signal inputted to each of the plurality of delay stages, generating a selection signal for phase determination by making a phase comparison between the output signal of the phase interpolator and a reference clock signal, transferring input signals for a next stage by determining one of the first and second input signals corresponding to each of the plurality of delay stages and each of the plurality of phase blending signals as axes for interpolation in response to the selection signal, generating one of two signals outputted from a last delay stage as the output signal of the phase interpolator when stage operations for final phase determination are completed, and repeating the process until the stage operations for final phase determination are completed.
Thus, although the number of stages according to minimum delay stages required for desired interpolation is increased, area and current dissipation of the total circuit may be reduced because there are an equal number of inverters comprising each stage. Also, because it is easy to match the loading of the inverters comprising each stage, a linear output characteristic may be obtained regardless of an increase of the number of delay stages.
These and other features and aspects of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.